低延迟低抖动的FAST解码器设计与实现

doi:10.3969/j.issn.0255-8297.2023.04.014

应用科学学报 ›› 2023, Vol. 41 ›› Issue (4): 705-717.doi: 10.3969/j.issn.0255-8297.2023.04.014

低延迟低抖动的FAST解码器设计与实现

张曦煌^1,2, 丁楠¹, 柴志雷¹, 冯一飞¹, 叶钧超¹

1. 江南大学人工智能与计算机学院, 江苏无锡 214122;
2. 无锡太湖学院智能装备学院, 江苏无锡 214064

收稿日期:2021-12-16 发布日期:2023-08-02
通信作者: 张曦煌,教授,研究方向为计算机网络、分布式系统与应用。E-mail:18921160516@163.com E-mail:18921160516@163.com
基金资助:
国家自然科学基金（No. 61972180）资助

Implementing a FAST Decoder with Low Latency and Low Jitter

ZHANG Xihuang^1,2, DING Nan¹, CHAI Zhilei¹, FENG Yifei¹, YE Junchao¹

1. School of Artificial Intelligence and Computer Science, Jiangnan university, Wuxi 214122, Jiangsu, China;
2. School of Intelligent Equipment Engineering, Wuxi Taihu University, Wuxi 214064, Jiangsu, China

Received:2021-12-16 Published:2023-08-02

摘要/Abstract

摘要： 为了解决金融FAST (financial information exchange adapted for streaming)协议面临的纯软件解码延迟高，FPGA (field programmable gate array)硬件解码开发周期长、更新困难的问题，提出了基于OpenCL和HLS的硬件解码模式。通过对FAST数据解码的标记、切分、合并、解码模块进行流水优化，对切分和字段解码进行并行操作，将数据的输入输出改为流式接口减少I/O口的延时以及对切分数组进行分割映射等优化方式实现了解码过程低延迟、低抖动。实验结果表明，相比纯软件解码，本文提出的解码器处理速度提升了11倍，解码延迟缩短至1/6，抖动幅度控制在10 ns之内。相比传统HDL方式的FPGA定制硬件开发，开发效率可提升3～4倍，从而更好地满足产品更新换代的需求。

关键词: OpenCL, 低延迟低抖动, FAST协议解码, 高层次综合, 现场可编程门阵列

Abstract: In order to solve the problems of high delay of pure software decoding, long development period of FPGA (field programmable gate array) hardware decoding and difficult update of financial FAST (financial information exchange adapted for streaming) protocol, a hardware decoding mode based on OpenCL and HLS was proposed. By optimizing the marking, segmentation, merging, and decoding modules of FAST data decoding through pipelining, parallel operations are performed on segmentation and field decoding. The input and output of the data are changed to a streaming interface to reduce I/O port latency, and the segmentation and mapping of the array segmentation are carried out to achieve low latency and low jitter in the decoding process. Experimental results show that compared with pure software decoding, the processing speed of the proposed decoder is improved by 11 times, the decoding delay is shortened to 1/6, and the jitter amplitude is controlled within 10ns. Compared with the traditional HDL custom FPGA hardware development, the proposed approach improves development efficiency by 3～4 times, thus better meeting the needs of product updates.

Key words: OpenCL, low latency and low jitter, FAST (financial information exchange adapted for streaming) protocol decoding, high level synthesis, field programmable gate array (FPGA)

中图分类号:

P751.1

张曦煌, 丁楠, 柴志雷, 冯一飞, 叶钧超. 低延迟低抖动的FAST解码器设计与实现[J]. 应用科学学报, 2023, 41(4): 705-717.

ZHANG Xihuang, DING Nan, CHAI Zhilei, FENG Yifei, YE Junchao. Implementing a FAST Decoder with Low Latency and Low Jitter[J]. Journal of Applied Sciences, 2023, 41(4): 705-717.

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低延迟低抖动的FAST解码器设计与实现

Implementing a FAST Decoder with Low Latency and Low Jitter

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