针对应用场景中不同哈希算法乃至多哈希算法组合的高速计算需求,纯软件方式难以满足性能需求,基于FPGA或ASIC的硬件方式又面临灵活性不足的问题,设计了一种异构且加速端硬件可重构的哈希算法高能效计算系统。计算系统由算法硬件加速模块、数据传输模块、多线程管理模块实现,并且通过硬件的动态可重构设计提升了计算能效。实验结果表明,在Intel Stratix10 FPGA异构计算平台上,针对加解密计算,选择MD5、SHA-1、SHA-256、SHA-512和RIPEMD-160算法作为测试对象,所实现的系统相比Intel Core I7-10700CPU,最高可获得18.7倍的性能提升和34倍的能效提升,相比NVIDIA GTX 1650 SUPER GPU,最高可获得2倍的性能提升和5.6倍的能效提升。
[1] KAkARounTAs A P, ThEoDoRiDis G, LAopouLos T, et al. High-speed FPGA implementation of the SHA-1 hash function[C]//2005 IEEE Intelligent Data Acquisition and Advanced Computing Systems:Technology and Applications, 2005:211-215.
[2] JiAnG L H, WAnG Y L, ZhAo Q X, et al. Ultra high throughput architectures for SHA-1hash algorithm on FPGA[C]//2009 International Conference on Computational Intelligence and Software Engineering, 2009:1-4.
[3] 李磊,韩文报. FPGA上SHA-1算法的流水线结构实现[J].计算机科学, 2011, 38(7):58-60.Li L, HAn W B. Implementation of pipeline structure on FPGA for SHA-1[J]. Computer Scinece, 2011, 38(7):58-60.(in Chinese)
[4] WAnG P J, WAnG L, PAn W, et al. A high-throughput SHA-1 implementation on FPGA[C]//International Conference on Communication Technology(ICCT 2013 VII), 2013:234-243.
[5] KAhRi F, MEsTiRi H, BouALLEGuE B, et al. Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256[C]//2015 IEEE 12th International Multi-Conference on Systems, Signals&Devices(SSD15), 2015:1-5.
[6] Li M, Xu J F, YAnG X H, et al. Design and implementation of reconfigurable security hash algorithms based on FPGA[C]//2009 WASE International Conference on Information Engineering, 2009:381-384.
[7] 陈晓杰,周清雷,李斌.基于多核FPGA的压缩文件密码破译[J].计算机应用研究, 2020, 37(1):212-215, 220.ChEn X J, Zhou Q L, Li B. Password recovery for compressed file based on multi-FPGA[J].Application Research of Computers, 2020(1):212-215, 220.(in Chinese)
[8] 杜飞飞,张德学,王佃涛,等. BLAKE2b算法优化及OpenCL实现[J].小型微型计算机系统, 2019,40(11):2281-2284.Du F F, ZhAnG D X, WAnG D T, et al. Optimization and OpenCL implementation of BLAKE2b[J]. Journal of Chinese Computer Systems, 2019, 40(11):2281-2284.(in Chinese)
[9] 郑朝霞,田园,蔚然,等.小面积高性能的SHA-1/SHA-256/SM3 IP复用电路的设计[J].计算机工程与科学, 2015, 37(8):1417-1422.ZhEnG Z X, TiAn Y, WEi R, et al. An SHA-1/SHA-256/SM3 IP multiplexing circuit with small area and high performance[J]. Computer Engineering and Science, 2015, 37(8):1417-1422.(in Chinese)
[10] 苗佳.杂凑算法SM3/SHA256/SHA3的硬件设计与实现[D].北京:清华大学, 2018.
[11] Jin Z M, FinkEL H. Evaluation of MD5Hash kernel on OpenCL FPGA platform[C]//2018IEEE International Parallel and Distributed Processing Symposium Workshops(IPDPSW),2018:1026-1032.
[12] JAnik I, KhALiD M A S. Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL[C]//2016 IEEE 59th International Midwest Symposium on Circuits and Systems(MWSCAS), 2016:1-4.
[13] BEnsALEM H, BLAQuiÈRE Y, SAvARiA Y. Acceleration of the secure hash algorithm-256(SHA-256)on an FPGA-CPU cluster using OpenCL[C]//2021 IEEE International Symposium on Circuits and Systems(ISCAS), 2021:1-5.
[14] MERkLE R C. One way hash functions and DES[M]//Advances in CryptologyDCRYPTO'89 Proceedings. New York, NY:Springer New York, 1990:428-446.
[15] National Institute of Standards and Technology. FIPS PUB 180-4, secure Hash Standard(SHS)[S]. Gaithersburg:NIST, 2012:1-10.
[16] 吴健凤,郑博文,聂一,等.基于OpenCL的3DES算法FPGA加速器[J].计算机工程, 2021,47(12):147-155, 162.Wu J F, ZhEnG B W, NiE Y, et al. FPGA accelerator for 3DES algorithm based on OpenCL[J]. Computer Engineering, 2021, 47(12):147-155, 162.(in Chinese)
[17] KAELi D R, MisTRy P, SchAA D, et al. Heterogeneous computing with OpenCL 2.0[M]. San Francisco, CA:Morgan Kaufmann, 2015.
[18] Intel Stratix 10 GX/SX Device Overview[EB/OL].[2021-12-13]. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10-overview.pdf.
[19] Li C J, Zhou Q G, Liu Y L, et al. Cost-efficient data cryptographic engine based on FPGA[C]//2011 Fourth International Conference on Ubi-Media Computing, 2011:48-52.
[20] 汤煜,翁秀玲,王云峰. SHA-256哈希运算单元的硬件优化实现[J].中国集成电路, 2016, 25(5):26-31.TAnG Y, WEnG X L, WAnG Y. Hardware optimization of SHA-256 hash operation unit[J].China Integrated Circuit, 2016, 25(5):26-31.(in Chinese)
[21] Jin Z M, FinkEL H. Optimizing parallel reduction on OpenCL FPGA platformśa case study of frequent pattern compression[C]//2018 IEEE International Parallel and Distributed Processing Symposium Workshops(IPDPSW), 2018:27-35.
[22] KoRoBEynikov A. Effective implementation of łkuznyechikžblock cipher on FPGA with OpenCL platform[C]//2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering(EIConRus), 2019:1683-1686.
[23] 陈晓杰,周清雷,李斌.基于FPGA的7-Zip加密文档高能效口令恢复方法[J].计算机科学, 2020,47(1):321-328.ChEn X J, Zhou Q L, Li B. Energy-efficient password recovery method for 7-Zip document based on FPGA[J]. Computer Science, 2020, 47(1):321-328.(in Chinese)
[24] 贾海鹏,张云泉,袁良,等.基于OpenCL的Viola-Jones人脸检测算法性能优化研究[J].计算机学报, 2016, 39(9):1775-1789.JiA H P, ZhAnG Y Q, YuAn L, et al. Research of Viola-Jones face detection algorithm performance optimization based on OpenCL[J]. Chinese Journal of Computers, 2016, 39(9):1775-1789.(in Chinese)
[25] LAGnF F M E, GAnEsAn S. Securing CAN FD by implementing AES-128, SHA256, and Message Counter based on FPGA[C]//2021 IEEE International Conference on Electro Information Technology(EIT), 2021:91-96.
[26] PhAM H L, TRAn T H, PhAn T D, et al. Double SHA-256 hardware architecture with compact message expander for bitcoin mining[J]. IEEE Access, 2020, 8:139634-139646.
[27] 姚中原,潘恒,祝卫华,等.区块链物联网融合:研究现状与展望[J].应用科学学报, 2021, 39(1):174-184.YAo Z Y, PAn H, Zhu W H, et al. Convergence of blockchain and IoT:research status and prospect[J]. Journal of Applied Sciences, 2021, 39(1):174-184.(in Chinese)
