收稿日期: 2016-02-02
修回日期: 2016-04-24
网络出版日期: 2017-03-30
基金资助
国家自然科学基金（No.61371025，No.61274036）资助
Applying Gate Replacement Technique Based on Double Weights to Mitigate Circuit Aging
Received date: 2016-02-02
Revised date: 2016-04-24
Online published: 2017-03-30
在纳米工艺水平下，负偏置温度不稳定性（negative bias temperature instability，NBTI）成为影响集成电路可靠性的关键性因素.NBTI效应导致晶体管阈值电压增加，老化加剧，最终使电路时序违规.为了缓解电路的NBTI效应，定义了时延关键性权值和拓扑结构关键性权值.使用该双权值识别的关键门更加精确，并且考虑到了关键门的扇入门为非门的情况，即将非门视为单输入与非门，并将其替换为双输入与非门，从而能更加全面地防护关键门.应用基于双权值的门替换方法对基于45 nm晶体管工艺的ISCAS85基准电路实验结果显示：当电路时序余量为5%时，不考虑非门替换时电路的时延改善率为38.29%，考虑非门替换时电路的时延改善率为60.66%.
朱炯, 易茂祥, 张姚, 胡林聪, 刘小红, 梁华国 . 应用基于双权值的门替换方法缓解电路老化[J]. 应用科学学报, 2017 , 35(2) : 171 -180 . DOI: 10.3969/j.issn.0255-8297.2017.02.004
Negative bias temperature instability (NBTI) is a key factor affecting reliability of integrated circuits at the nanometer level. The NBTI effects increase transistor threshold voltage, cause aging of the circuit, and result in the circuit timing violations. To mitigate the NBTI effects of the circuit, we define delay weight and topology weight to identify critical gates more precisely. We also consider the case that the fan-in gate of a critical gate is INV. We take it as NAND1, and use NAND2 to replace INV. Thus the critical gates can be better protected. Experiments on ISCAS85 benchmark circuits based on a 45 nm transistor model show that, when the circuit timing margin is 5%, and the gate replacement technique based on double weights is used, the average delay improvement is 38.29% without considering replacement of INV. The average delay improvement is increased to 60.66% when considering INV replacement.
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