收稿日期: 2010-12-28
修回日期: 2011-09-03
网络出版日期: 2012-05-30
基金资助
国家自然科学基金(No.60576033);国家“863”高技术研究发展计划基金(No.2007AA04Z423 ,No.2006AA01Z106);福建省
自然科学基金(No.2008J04001);厦门市科技项目基金(No.3502Z20083031)资助
High-Speed Arbitrarily Distributed Pseudo-random Number Generator Based on FPGA
Received date: 2010-12-28
Revised date: 2011-09-03
Online published: 2012-05-30
刘沛华1, 鲁华祥1, 龚国良1, 刘文鹏1, 陈天翔2 . 基于FPGA的高速任意分布伪随机数发生器[J]. 应用科学学报, 2012 , 30(3) : 306 -310 . DOI: 10.3969/j.issn.0255-8297.2012.03.015
Acceptance-rejection is a widely used method to generate arbitrarily distributed pseudo-random numbers from uniformly distributed pseudo-random numbers. This paper proposes a method to improve accepting efficiency. The method transforms samples that are discarded in the original method into acceptable ones to improve efficiency. With the improved acceptance-rejection method, an arbitrarily distributed pseudo-random number generator is designed, which uses a linear feedback shift register to produce uniformly distributed pseudo-random numbers, and then uses the improved acceptance-rejection scheme to generate arbitrarily distributed pseudo-random numbers. The design is implemented on FPGA. The experimental results show that the design has high output efficiency and wide applicability.
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