论文

基于FPGA的高速任意分布伪随机数发生器

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  • 1. 中国科学院半导体研究所神经网络实验室,北京100083
    2. 厦门理工大学电子与电气工程系,福建厦门361024
鲁华祥,研究员,博导,研究方向:人工神经网络软硬件和智能信息处理,E-mail:luhx@semi.ac.cn

收稿日期: 2010-12-28

  修回日期: 2011-09-03

  网络出版日期: 2012-05-30

基金资助

国家自然科学基金(No.60576033);国家“863”高技术研究发展计划基金(No.2007AA04Z423 ,No.2006AA01Z106);福建省
自然科学基金(No.2008J04001);厦门市科技项目基金(No.3502Z20083031)资助

High-Speed Arbitrarily Distributed Pseudo-random Number Generator Based on FPGA

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  • 1. Laboratory of Artificial Neural Networks, Institute of Semiconductors,Chinese Academy of Sciences, Beijing 100083, China
    2. Faculty of Electronic and Electric Engineering, Xiamen University of Technology,Xiamen 361024, Fujian Province, China

Received date: 2010-12-28

  Revised date: 2011-09-03

  Online published: 2012-05-30

摘要

舍选法是广泛应用的基于均匀分布产生任意分布随机数序列的方法. 文中针对舍选法接受效率低的缺点提出一种改进方案,将舍选法中本该舍弃的样本通过映射转换成可接受的样本,提高了接受效率. 根据改进的舍选法设计了一种任意分布的伪随机数发生器,利用线性反馈移位寄存器产生均匀分布随机数序列,在此基础上运用改进舍选法产生任意分布随机数,并在现场可编程门阵列(field programmable gate array,FPGA)上实现. 对不同分布的实验结果表明,该设计具有输出效率高、通用性强的优点.

本文引用格式

刘沛华1, 鲁华祥1, 龚国良1, 刘文鹏1, 陈天翔2 . 基于FPGA的高速任意分布伪随机数发生器[J]. 应用科学学报, 2012 , 30(3) : 306 -310 . DOI: 10.3969/j.issn.0255-8297.2012.03.015

Abstract

 Acceptance-rejection is a widely used method to generate arbitrarily distributed pseudo-random numbers from uniformly distributed pseudo-random numbers. This paper proposes a method to improve accepting efficiency. The method transforms samples that are discarded in the original method into acceptable ones to improve efficiency. With the improved acceptance-rejection method, an arbitrarily distributed pseudo-random number generator is designed, which uses a linear feedback shift register to produce uniformly distributed pseudo-random numbers, and then uses the improved acceptance-rejection scheme to generate arbitrarily distributed pseudo-random numbers. The design is implemented on FPGA. The experimental results show that the design has high output efficiency and wide applicability.

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