| [1] APPELS J , VAES H, VERHOEVEN J. High voltage thin layer devices[J]. Electron Devices Meeting, 1979, 25: 238-241.[2] APPELS J A, COLLET M G, HART P A H, VAES H M J, VERHOEVEN J F C M. Thin layer high voltage devices[J]. Philips Journal of Research, 1980, 35(1): 1-5.[3] IMAM Mohamed, QUDDUS Mohammed, ADAMS Jim, HOSSAIN Zia. Efficacy of charge sharing in reshaping the surface electric field in high voltage lateral RESURF devices[J]. IEEE Transactions Electron Devices, 2004, 51(1): 141-148[4] OROUJI A A, MEHRAD M. Breakdown voltage improvement of LDMOSs by charge balancing: an inserted P-layer in trench oxide (IPT-LDMOS) [J]. Superlattices and Microstructures, 2012, 51: 412-420[5] SHIMAMOTO Satoshi, YANAGIDA Yohei, SHIRAKAWA Shinji, MIYAKOSHI Kenji, OSHIMA Takayuki, SAKANO Junichi, WADA Shinichiro, NOGUCHI Junji. High-performance p-channel LDMOS transistors and wide-range voltage platform technology using novel p-channel structure[J]. IEEE Transactions on Electron Devices, 2013, 60(1): 360-365[6] LI Q, WANG W D, LI H O, WEI X M. High voltage silicon power device structure with substrate bias[J]. Electronics Letters, 2011, 47(25): 1394-1396[7] CHANG Yang Hua, CHANG Chia Hao. Improving an LDMOST by variation of lateral doping on epitaxial-layer drift region [J]. Microelectronics Reliability, 2011, 51: 2059-2063[8] LI Xiaogang, FENG Zhicheng, ZHANG Zhengyuan, HU Mingyu. A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices[J]. Journal of Semiconductors , 2009 , 30(3): 034005-1[9] Sel Colak S. Effects of drift region parameters on the static properties of power LDMOST[J]. IEEE Transactions on electron devices, 1981, ED-28(12): 1455-1465[10] CHUNG Sang Koo, HAN Seung Youp, SHIN Jin Cheol, et al. An analytical model for minimum drift region length of SOI RESURF diodes[J]. IEEE Electron Device Letters, 1996, 17(1): 22-24[11] CHUNG Sang Koo, HAN Seung Youp. Analytical model for the surface field distribution of SOI RESURF devices [J]. IEEE Transactions on Electron Devices, 1998, 45(6): 1374-1376[12] SUN Weifeng, SHI Longxing. Analytical models for the surface potential and electrical field distribution of bulk-silicon RESURF devices[J]. Solid-State Electronics, 2004, 48: 799-805[13] CORTÉS I, TOULON G, MORANCHO F, HUGONNARD-BRUYERE E, VILLARD B, TOREN W J. Analysis and optimization of lateral thin-film Silicon-on-insulator (SOI) MOSFET transistors [J]. Microelectronics Reliability, 2012, 52: 503-508[14] HE Jin, ZHANG Xing. Quasi-2-D analytical model for the surface field distribution and optimization of RESURF LDMOS transistor[J]. Microelectronics Journal, 2001, 32: 655-663[15] CHANG Yang Hua, LIN Shih Wei, CHANG Chia Hao. Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate[J]. Microelectronics Reliability, 2010, 50:949-953 [16] Shyam HARDIKAR S, Ramakrishna TADIKONDA R, David W. GREEN D W, Konstantin V. VERSHININ K V, Ekkanath Madathil Sankara Narayanan. Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping [J]. IEEE Transactions on Electron Devices, 2004, 51(12): 2223-2228[17] VESTLING L, OLSSON J, EKLUND K H. Drift region optimization of lateral RESURF devices[J]. Solid-State Electronics, 2002, 46: 1177-1184[18] MOENS P, van den BOSCH G. Reliability assessment of integrated power transistors: lateral DMOS versus vertical DMOS [J]. Microelectronics Reliability, 2008, 48: 1300-1305[19] DUAN Baoxing, YANG Yintang, ZHANG Bo. High voltage REBULF LDMOS with N+ buried layer[J]. Solid-State Electronics, 2010, 54: 685–688 |
