Abstract: Test pattern generation for integrated circuits is an important and complex problem. An optimization method of test pattern generation for digital circuits is proposed in this paper. In the method, a characteristic function for each basic gate circuit and the constrained network for the circuit under test (CUT) are defined, the test patterns for a fault can be obtained by means of a simulated annealing algorithm. A new algorithm, namely annealing descent algorithm(SDA), is presented, which enhance the performance of conventional simulated annealing method, and accelerate the test generation process further.

Key words: digital circuits, test generation, optimization, descent algorthms, simulated annealing