Abstract: In this paper, we propose a new method to solve the peak power problem by partitioning the operation of flip-flops in the same clock domain during the scan test. This method need not regenerate test patterns so that the test patterns generated before partition can be reused. The experiments show that the proposed method can reduce the consumption of peak power, ave-rage power and energy simultaneously with a slight increase of test time.

Key words: design-for-test, test, scan, peak power