Abstract:

Due to the complexity of the popular asymmetric-key encryption algorithm RSA, the hardware implementation
has a too large overhead to be used in resource-constrained systems. In order to solve this problem, an RSA
encryption engine based on 256 bit data width processor is designed, which greatly reduces the area required by RSA.
Synthesis results show that, in addition to the basic function implementation, the improved RSA design reduces the area
by 55.63% with respect to SLE66CX160S of Siemens. It has 24 k gates count with a maximum clock frequency of 100
MHz. The implemented RSA engine meets the design requirements.

Key words: VLSI, RSA algorithm, modular multiplication, modular exponentiation