In order to solve the problems of high delay of pure software decoding, long development period of FPGA (field programmable gate array) hardware decoding and difficult update of financial FAST (financial information exchange adapted for streaming) protocol, a hardware decoding mode based on OpenCL and HLS was proposed. By optimizing the marking, segmentation, merging, and decoding modules of FAST data decoding through pipelining, parallel operations are performed on segmentation and field decoding. The input and output of the data are changed to a streaming interface to reduce I/O port latency, and the segmentation and mapping of the array segmentation are carried out to achieve low latency and low jitter in the decoding process. Experimental results show that compared with pure software decoding, the processing speed of the proposed decoder is improved by 11 times, the decoding delay is shortened to 1/6, and the jitter amplitude is controlled within 10ns. Compared with the traditional HDL custom FPGA hardware development, the proposed approach improves development efficiency by 3～4 times, thus better meeting the needs of product updates.
ZHANG Xihuang, DING Nan, CHAI Zhilei, FENG Yifei, YE Junchao
. Implementing a FAST Decoder with Low Latency and Low Jitter[J]. Journal of Applied Sciences, 2023
, 41(4)
: 705
-717
.
DOI: 10.3969/j.issn.0255-8297.2023.04.014
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