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应用科学学报 ›› 2010, Vol. 28 ›› Issue (6): 633-638.doi: 10.3969/j.issn.0255-8297.2010.06.013

• 电子技术 • 上一篇    下一篇

低资源消耗多边类型LDPC码译码器的FPGA实现

谢东福1， 王琳2， 陈平平1   

  1. 1. 厦门大学电子工程系，福建厦门361008
    2. 厦门大学通信工程系，福建厦门361008
  • 收稿日期:2010-07-15 修回日期:2010-10-09 出版日期:2010-11-26 发布日期:2010-11-25
  • 作者简介:谢东福，博士生，研究方向：通信集成电路设计，E-mail: dawnforever@gmail.com；王琳，博导，研究方向：通信物理层算法设计分析与实现，E-mail: wanglin@xmu.edu.cn
  • 基金资助:

    国家自然科学基金(No.60972053)资助

Decoder with Low Resource Overhead for Multi-edge Type LDPC Codes Based on Cache

  1. 1. Department of Electronic engineering, Xiamen University, Xiamen 361008, Fujian Province, China
    2. Department of Communication Engineering, Xiamen University, Xiamen 361008, Fujian Province, China
  • Received:2010-07-15 Revised:2010-10-09 Online:2010-11-26 Published:2010-11-25

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摘要：

以低资源消耗和低功耗应用为基础设计了多边类型低密度奇偶校验码译码器. 该译码器采用缓存有效连通校验点计算单元与变量点计算单元. 分析和实验表明，与传统的部分并行译码器结构相比，若校验矩阵不具有特殊结构，该译码器可以减少近50% 的用于存储迭代信息的存储器；节约近90% 的用于传输迭代信息的多路选择器；节省80% 的变量点计算单元.

关键词: 多边类型, 低密度奇偶校验码, 译码器, 缓存, 现场可编程逻辑阵列

Abstract:

To study low cost and low power applications, we propose a decoding architecture with low resource overhead for multi-edge-type low density parity check (LDPC) codes. The architecture links the check node computed unit and variable node computed unit by cache. The analysis and experiments show that, compared with the traditional partial parallel decoding architecture, the decoding architecture described in this paper cuts about 50% RAM for storing iterative information when the check matrix is random, about 90% MUX for transmitting iterative information, and about 80% variable node computation unit for generating iterative information transmitted form variable nodes to check nodes.

Key words: multi-edge-type, low density parity check codes, decoder, cache, field programmable gate array

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