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应用科学学报 ›› 2006, Vol. 24 ›› Issue (3): 240-244.

• 论文 • 上一篇    下一篇

过采样技术CDR分析及应用

尹勇生1, 胡永华1, 高明伦1,2   

  1. 1. 合肥工业大学微电子设计研究所, 安徽合肥 230009;
    2. 南京大学物理系微电子设计研究所, 江苏南京 210093
  • 收稿日期:2005-01-12 修回日期:2005-06-15 出版日期:2006-05-31 发布日期:2006-05-31
  • 作者简介:尹勇生,博士生,研究方向:可重构计算与VLSI设计,E-mail:yinyongsheng@hfut.edu.cn;高明伦,教授,博导,研究方向:VLSI设计理论和方法,E-mail:gaominglun@hfut.edu.cn
  • 基金资助:
    国家自然科学基金资助项目(90307011)

Analysis and Application of CDR Circuit Using Oversampling

YIN Yong-sheng1, HU Yong-hua1, GAO Ming-lun1,2   

  1. 1. Institue of Very Large Scale Integration Design, Hefei University of Technology, Hefei 230009, China;
    2. Institute of Very Large Scale Integration Design, Nanjing University, Nanjing 210093, China
  • Received:2005-01-12 Revised:2005-06-15 Online:2006-05-31 Published:2006-05-31

PDF

153

被引次数

46

摘要： 在串行数据通信领域中,过采样法CDR是一种便于单芯片集成、具有快速同步特点的低成本数字技术.文中经过理论分析给出了一个基于过采样技术的时钟数据恢复电路(CDR)设计.该设计采用4倍过采样技术并使用多数判决规则从输入数据位流中提取时钟和恢复数据.实验结果表明在至少1/4位宽抖动容差范围内,传输系统满足面向USB应用的差错率设计要求.

关键词: 过采样, 不归零反转, 时钟数据恢复

Abstract: In serial data communication domain, clock and data recovery (CDR) using oversampling is a low-cost "fast retiming" technique that can be implemented as monolithic circuits using the standard digital CMOS process.This paper presents a CDR circuit based on oversampling.The design uses 4x oversampling rate, that is, an FSM is constructed to get four equidistant samples per bit cell.Data are then extracted from input data dreams using a majority decision algorithm.Simulation results show that the specified bit error rate oriented to USB2.0 is achieved in the presence of at least 1/4 bit cell jitter.It is believed that the analysis and design technique are useful for other serial data communication of computer peripherals.

Key words: NRZI (non return to zero invert), oversampling, clock and data recovery

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