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浮定点转换与SoC定点加速器字长协同设计研究

周凡;时龙兴;杨军;张宇;高谷刚   

  1. 东南大学 国家专用集成电路系统工程技术研究中心，江苏 南京 210096
  • 收稿日期:2006-05-25 修回日期:2006-09-15 出版日期:2007-03-20 发布日期:2007-03-20

Determining Word Length of FixedPoint Accelerator in SOC Based on FloatPoint to FixedPoint Conversion

ZHOU Fan;SHI Long xing;YANG Jun;ZHANG Yu;GAO Gu gang   

  1. National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
  • Received:2006-05-25 Revised:2006-09-15 Online:2007-03-20 Published:2007-03-20

被引次数

2

摘要： 在SoC (system on chip)设计中，许多通信、多媒体等高计算复杂度应用常需要构建专用的硬件加速器，用以提高性能，降低功耗.而对于片内SoC专属硬件加速器，其运算单元和片内存储体的字长与芯片面积、功耗等休戚相关.文中提出了一种新颖的基于统计分析浮定点转换的定点硬件加速器字长设计方法，该方法同时考虑硬件设计和浮定点算法转换，利用统计参数在数学层面上求解计算信噪比，避免了采用穷举法选择最优浮定点转换算法，极大地减小了计算复杂度，有效地降低芯片面积、功耗和成本，从而能在没有DSP协处理器的低成本RISC处理器核SoC芯片上运行高计算复杂度应用.

关键词: 硬件加速器, 定点, 系统芯片, 字长, 信噪比, 统计分析

Abstract: Many multimedia and communication applications require dedicated hardware accelerator to achieve acceptable performance and cost in SoC. The word length of the computation unit or memory in hardware accelerator is important to the chip area and power consumption. This paper proposes a novel method for the design of word length of fixed point hardware accelerator based on float point to fixed point conversion from statistical perspective. The proposed approaches take into account the hardware architecture design and the software conversion together, solving the problem on a mathematical layer. In any case, the method can greatly reduce computation load, and implement multimedia calculations of high computational complexity without using a DSP chip.

Key words: hardware accelerator, statistical analysis, fixed point, SoC, word length, SNR