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应用科学学报 ›› 2007, Vol. 25 ›› Issue (5): 475-475 .

• 论文 • 上一篇    下一篇

一种高效的多级递归提升离散小波变换的VLSI架构

曹 鹏 王 超 李 杰   

  1. 东南大学 国家专用集成电路系统工程技术研究中心,江苏 南京210096
  • 收稿日期:2007-05-08 修回日期:2007-07-06 出版日期:2007-09-30 发布日期:2007-09-30

Effective VLSI Architecture for Multi-level Recursive Discrete Lifting Wavelet Transform

CAO Peng , WANG Chao, LI Jie   

  1. National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
  • Received:2007-05-08 Revised:2007-07-06 Online:2007-09-30 Published:2007-09-30

被引次数

2

摘要： 提出了一种基于提升模式的递归算法实现多级离散小波变换，该算法通过交错计算各级小波变换，提高了运算效率。文中以9/7提升小波为例，给出了相应的多级离散小波变换架构。该架构在Altera的StratixⅡEP2S60 FPGA上得到了综合验证，运行频率达到了80MHz。分析和比较表明,该架构能够显著减少多级离散小波变换的运行时间，提高硬件利用率，减少存储器大小，具有速度快、面积小、功耗低等优点。和已有的架构相比，硬件利用率最大可提高22%。

关键词: 离散小波变换, VLSI, 提升, 递归

Abstract: In this paper, a lifting-based recursive algorithm (LRA) is proposed for multi-level discrete wavelet transform (DWT) by interleaving calculation of different level DWT. As an example, we propose an architecture for multi-level 9/7 DWT with lifting scheme by using LRA.It is synthesized and implemented for Altera’s StratixⅡFPGA EP2S60 and can work under a clock frequency of 80 MHz. Performance analysis and comparison results demonstrate that the proposed architecture have good performance in terms of computing time, hardware utilization, and power consumption. Compared to other existing architectures,the hardware utilization of rate is up to 22% higher.

Key words: discrete wavelet transform (DWT), VLSI, lifting, recursive