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应用科学学报

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同时多线程微处理器分布式保留站结构的数据流技术

杨洪斌，吴 悦，刘权胜
  

  1. 上海大学 计算机工程与科学学院，上海 200072
  • 收稿日期:2007-06-21 修回日期:2007-12-14 出版日期:2008-03-31 发布日期:2008-03-31

Distributed Reservation Architecture of Simultaneous Multithreading Processor

YANG Hong-bin, WU Yue, LIU Quan-sheng   

  1. School of Computer Engineering and Science, Shanghai University, Shanghai 200072, China
  • Received:2007-06-21 Revised:2007-12-14 Online:2008-03-31 Published:2008-03-31

被引次数

20

摘要： 为提高同时多线程微处理器数据流指令高效并行执行性能，提出一种7个部分组成的分布式保留站结构。分布式保留站结构的同时多线程微处理器中采用了线程独占重排序缓冲的提交机制及能够快速访问并且具有硬件复杂度低特点的寄存器堆。两线程指令执行的结果表明其并行度得到明显提高。对保留站、重排序缓冲提交机制及寄存器堆协同工作的功能进行验证与仿真，用综合工具完成逻辑综合。

关键词: 同时多线程微处理器, 保留站, 重排序缓冲, 寄存器, 执行部件

Abstract: To improve the high-efficiency parallel processing performance of data flow instruction of a simultaneous multithreading processor, a 7-part distributed reservation architecture is presented. The simultaneous multithreading processor uses committing mechanism for each thread with single reorder buffer and register with smart speed and low complexity of hardware. The parallel degree of data flow instruction is improved for two threads. The function of reservation, committing mechanism and register is validated and simulated. These units are synthesized.

Key words: simultaneous multithreading processor, reservation, reorder buffer, register, function unit