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基于排队模型的总线缓冲估计

吴旭凡 杨军
  

  1. 东南大学 国家专用集成电路系统工程技术研究中心，江苏 南京 210096
  • 收稿日期:2004-10-03 修回日期:2004-08-29 出版日期:2006-01-31 发布日期:2006-01-31

Queuing Network Based Model for Bus Buffer Estimation

WU Xu-fan, YANG Jun   

  1. National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China
  • Received:2004-10-03 Revised:2004-08-29 Online:2006-01-31 Published:2006-01-31

被引次数

1

摘要： 根据嵌入式微处理器结构特征，提出了一种基于具有优先级排队模型的总线接口缓冲估计方法。通过对系统的抽象，建立了总线缓冲的排队模型，然后给出详细的估计步骤。最后对结果进行了理论分析，并针对实例应用该方法进行了缓冲容量估计，估计结果同高层仿真结果进行了比较，证明了该方法的有效性。

关键词: 嵌入式微处理器, 排队模型, 片上总线, 缓冲

Abstract: A method based on a priority-ranked queuing network model for bus buffer estimation is proposed from the characteristics of the embedded microprocessor structure. By summarizing the system, a queuing network model of bus buffer is built. Detailed step of estimating is then presented. Results are analyzed, and an example constructed based on a real application. Comparing the results with high-level model simulation, validity of the method is proved.

Key words:

embedded microprocessor, queuing network model, on-chip bus, buffer