应用科学学报 ›› 2010, Vol. 28 ›› Issue (1): 65-71.

• 计算机科学与应用 • 上一篇    下一篇

小面积RSA加密引擎的硬件实现

刘政林, 郭文平, 霍文捷, 邹雪城   

  1. 华中科技大学电子科学与技术系,武汉430074
  • 收稿日期:2009-08-10 修回日期:2009-11-05 出版日期:2010-01-20 发布日期:2010-01-20
  • 作者简介:刘政林,博士,副教授,研究方向:系统芯片设计和嵌入式系统安全,E-mail: liuzhenglin@mail.hust.edu.cn;邹雪城,教授, 博导,研究方向:超大规模集成电路的研究与设计、微电子与微光子学以及集成微纳电子器件与系统,E-mail: estxczou@mail.hust.edu.cn
  • 基金资助:

    国家自然科学基金(No.60973034);新世纪优秀人才支持计划基金(No.NCET-07-0328)资助

Small-Area Implementation of RSA Encryption Engine

LIU Zheng-lin, GUO Wen-ping, HUO Wen-jie, ZOU Xue-cheng   

  1. Department of Electronic Science and Technology, Huazhong University of Science and Technology,Wuhan 430074, China
  • Received:2009-08-10 Revised:2009-11-05 Online:2010-01-20 Published:2010-01-20

摘要:

RSA非对称密钥算法因其算法的复杂性,硬件实现开销一直较大. 针对该问题,提出采用256位数据宽度处理的方式代替传统的1 024位数据宽度处理,通过折叠数据通道,精简电路结构,并使用片内静态随机存储器(SRAM)减小实现面积,实现了应用于资源受限环境下的小面积RSA硬件加密引擎. 采用华虹NEC0.25 mm工艺实现该电路,整个设计规模约为24 k等效门,最大工作频率为100MHz,相比于实用芯片西门子SLE66CX160S,本实现的面积缩小了55.63%.

关键词: 超大规模集成电路, RSA算法, 模乘, 模幂

Abstract:

Due to the complexity of the popular asymmetric-key encryption algorithm RSA, the hardware implementation
has a too large overhead to be used in resource-constrained systems. In order to solve this problem, an RSA
encryption engine based on 256 bit data width processor is designed, which greatly reduces the area required by RSA.
Synthesis results show that, in addition to the basic function implementation, the improved RSA design reduces the area
by 55.63% with respect to SLE66CX160S of Siemens. It has 24 k gates count with a maximum clock frequency of 100
MHz. The implemented RSA engine meets the design requirements.

Key words: VLSI, RSA algorithm, modular multiplication, modular exponentiation

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