中文

Journal of Applied Sciences ›› 2010, Vol. 28 ›› Issue (4): 399-405.doi: 10.3969/j.issn.0255-8297.2010.04.012

• Electronic Engineering • Previous Articles     Next Articles

CHEN Tian1, LIANG Hua-guo1, ZHANG Min-sheng1, WANG Wei1;2, YI Mao-xiang1   

  1. 1. School of Computer and Information, Hefei University of Technology, Hefei 230009, China
    2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100090, China
  • Received:2009-05-25 Revised:2010-06-20 Online:2010-07-23 Published:2010-07-23

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Abstract:

A test pattern generation method for low power test is proposed. The deterministic set of test cubesis embedded into the test pattern sequences generated with a segment fixing folding counter. This test pattern generator relies on the random access scan (RAS) architecture. In RAS, a new test pattern is directly loaded into scan cells without a shift procedure. Experimental results on ISCAS-89 benchmark circuits demonstrate
that this scheme can reduce data volume, application time and power consumption of the test simultaneously.

Key words: segment fixing, random access scan, data compression, low power

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