中文

Journal of Applied Sciences ›› 2013, Vol. 31 ›› Issue (5): 537-543.doi: 10.3969/j.issn.0255-8297.2013.05.015

• Electronic Engineering • Previous Articles     Next Articles

Gate Replacement with Input Vector Constraint to Mitigate Circuit Aging

LI Yang1,2, LIANG Hua-guo3, TAO Zhi-yong1   

  1. 1. School of Computer and Information, Hefei University of Technology, Hefei 230009, China
    2. Department of Information, Jiangsu Vocational College of Business, Nantong 226000, Jiangsu Province, China
    3. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, China
  • Received:2012-12-25 Revised:2013-06-22 Online:2013-09-26 Published:2013-06-22

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Abstract: To mitigate NBTI-induced circuit aging and enhance circuit reliability, gate replacement with input vector constraint during standby is proposed. The potential critical paths are found by using dynamic and static NBTI-aware static timing analysis. The critical gates are then found by considering path correlation. An
input vector is generated to make the critical gates in a recovery phase to the largest extent. Gate replacement is applied to the critical gates beyond control. Experiment results with ISCAS benchmark circuit demonstrate that the average gate replacement rate is reduced to 9.68%, and the average delay improvement is increased to 39.65% with the circuit timing margin 5%.

Key words: circuit aging, NBTI, input vector, gate replacement

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