Abstract: In this paper, a family of systolic designs for convolution computation classified into two categories, convolution arrays with and without global data communication, is proposed. Systolic architecture, which permits multiple computations for each memory access, can speed up execution of compute-bound problems without increasing I/O requirements.
A lot of compute-bound computation problems can be solved by systolic architecture systems, onvolution computation problems can be used in the study of systolic structure. The convolution computation can be implemented efficiently using the systolic architecture systems which are consisted of several single-chip processors served as processing elements.