低失真与高速采样保持电路的设计

XIA Wei-yi, WU Jian-hui

National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

Received:2004-04-19 Revised:2004-06-18 Online:2005-03-31 Published:2005-03-31

CLC Number:

XIA Wei-yi, WU Jian-hui. The Design of Low Distortion High Speed Sample/Hold Circuit[J]. Journal of Applied Sciences, 2005, 23(2): 183-186.

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