Abstract: In serial data communication domain, clock and data recovery (CDR) using oversampling is a low-cost "fast retiming" technique that can be implemented as monolithic circuits using the standard digital CMOS process.This paper presents a CDR circuit based on oversampling.The design uses 4x oversampling rate, that is, an FSM is constructed to get four equidistant samples per bit cell.Data are then extracted from input data dreams using a majority decision algorithm.Simulation results show that the specified bit error rate oriented to USB2.0 is achieved in the presence of at least 1/4 bit cell jitter.It is believed that the analysis and design technique are useful for other serial data communication of computer peripherals.

Key words: NRZI (non return to zero invert), oversampling, clock and data recovery