Abstract: Many multimedia and communication applications require dedicated hardware accelerator to achieve acceptable performance and cost in SoC. The word length of the computation unit or memory in hardware accelerator is important to the chip area and power consumption. This paper proposes a novel method for the design of word length of fixed point hardware accelerator based on float point to fixed point conversion from statistical perspective. The proposed approaches take into account the hardware architecture design and the software conversion together, solving the problem on a mathematical layer. In any case, the method can greatly reduce computation load, and implement multimedia calculations of high computational complexity without using a DSP chip.

Key words: hardware accelerator, statistical analysis, fixed point, SoC, word length, SNR