Abstract: To improve the high-efficiency parallel processing performance of data flow instruction of a simultaneous multithreading processor, a 7-part distributed reservation architecture is presented. The simultaneous multithreading processor uses committing mechanism for each thread with single reorder buffer and register with smart speed and low complexity of hardware. The parallel degree of data flow instruction is improved for two threads. The function of reservation, committing mechanism and register is validated and simulated. These units are synthesized.

Key words: simultaneous multithreading processor, reservation, reorder buffer, register, function unit