Abstract: A method based on a priority-ranked queuing network model for bus buffer estimation is proposed from the characteristics of the embedded microprocessor structure. By summarizing the system, a queuing network model of bus buffer is built. Detailed step of estimating is then presented. Results are analyzed, and an example constructed based on a real application. Comparing the results with high-level model simulation, validity of the method is proved.

Key words:

embedded microprocessor, queuing network model, on-chip bus, buffer