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Journal of Applied Sciences

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Design of an Improved Current Summing Reference


ZHANG Yao-zhong, WU Jian-hui, DING Jia-ping, LONG Shan-li   

  1. National ASIC System Engineering Center, Southeast University, Nanjing 210096, China
  • Received:2004-09-27 Revised:2004-12-06 Online:2006-01-31 Published:2006-01-31

Abstract:

A CMOS band-gap current summing reference is designed, which is self-biasd with a cascode structure. Hspice simulation with a Chart CMOS 0.35μm and 5V power supply shows that, within ?40?C ~ +85?C, the temperature coefficient is 15.2ppm/?C, and the power supply restrain ratio is ?51.8dB.

Key words:

current reference, current summing, temperature performance, power supply restrain ratio, self-bias