应用基于双权值的门替换方法缓解电路老化

doi:10.3969/j.issn.0255-8297.2017.02.004

Abstract

Abstract:

Negative bias temperature instability (NBTI) is a key factor affecting reliability of integrated circuits at the nanometer level. The NBTI effects increase transistor threshold voltage, cause aging of the circuit, and result in the circuit timing violations. To mitigate the NBTI effects of the circuit, we define delay weight and topology weight to identify critical gates more precisely. We also consider the case that the fan-in gate of a critical gate is INV. We take it as NAND1, and use NAND2 to replace INV. Thus the critical gates can be better protected. Experiments on ISCAS85 benchmark circuits based on a 45 nm transistor model show that, when the circuit timing margin is 5%, and the gate replacement technique based on double weights is used, the average delay improvement is 38.29% without considering replacement of INV. The average delay improvement is increased to 60.66% when considering INV replacement.

Key words: negative bias temperature instability (NBTI), critical gate, replacement of INV, circuit timing violation, double weight

CLC Number:

TN47

ZHU Jiong, YI Mao-xiang, ZHANG Yao, HU Lin-cong, LIU Xiao-hong, LIANG Hua-guo. Applying Gate Replacement Technique Based on Double Weights to Mitigate Circuit Aging[J]. Journal of Applied Sciences, 2017, 35(2): 171-180.

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Applying Gate Replacement Technique Based on Double Weights to Mitigate Circuit Aging

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