Negative bias temperature instability (NBTI) is a key factor affecting reliability of integrated circuits at the nanometer level. The NBTI effects increase transistor threshold voltage, cause aging of the circuit, and result in the circuit timing violations. To mitigate the NBTI effects of the circuit, we define delay weight and topology weight to identify critical gates more precisely. We also consider the case that the fan-in gate of a critical gate is INV. We take it as NAND1, and use NAND2 to replace INV. Thus the critical gates can be better protected. Experiments on ISCAS85 benchmark circuits based on a 45 nm transistor model show that, when the circuit timing margin is 5%, and the gate replacement technique based on double weights is used, the average delay improvement is 38.29% without considering replacement of INV. The average delay improvement is increased to 60.66% when considering INV replacement.
