Abstract: The EXOR-sum-of-products (ESOP) is the most general form of 2-level AND-EXOR networks, it usually requires fewer products than Reed-Muller canonic expressions. A new method of design for testability (DFT) is presented in the paper, which employs AND gates and XOR gates tree to realize the ESOP expression of arbitrary logic functions. The method is able to reduce the delay in the circuits as compared with the approaches using XOR gates cascade. A universal test set which detects multiple faults in the circuit realization is given, it can be generated easily and is independent of the logic function realized. The results have considerable significance on the detection and testable design of multiple faults in the digital circuits.

Key words: logic functions, testable design, digital circuits, multiple faults