A test pattern generation method for low power test is proposed. The deterministic set of test cubesis embedded into the test pattern sequences generated with a segment fixing folding counter. This test pattern generator relies on the random access scan (RAS) architecture. In RAS, a new test pattern is directly loaded into scan cells without a shift procedure. Experimental results on ISCAS-89 benchmark circuits demonstrate
that this scheme can reduce data volume, application time and power consumption of the test simultaneously.