K=9卷积码的Viterbi译码算法及其FPGA实现

应用科学学报 ›› 1998, Vol. 16 ›› Issue (2): 149-156.

K=9卷积码的Viterbi译码算法及其FPGA实现

胡爱群, 庞康, 苏杰

东南大学

收稿日期:1996-06-29 修回日期:1997-03-25 出版日期:1998-06-30 发布日期:1998-06-30
作者简介:胡爱群:副教授,东南大学无线电系,南京 210096
基金资助:
国家863计划

Viterbi Decoding Algorithm and Its FPGA Implementation for K=9 Convolutional Codes

HU AIQUN, PANG KANG, SU JIE

Southeast University, Nanjing 210096

Received:1996-06-29 Revised:1997-03-25 Online:1998-06-30 Published:1998-06-30

摘要/Abstract

摘要： 探讨了CDMA数字移动通信中的差错控制问题,研究用约束度K=9的卷积编码和最大似然Viterbi译码的差错控制方案.在Viterbi译码算法中,提出了原位运算度量、保存路径转移过程和循环存取幸存路径等方法,能有效地减少存储量、降低功耗,使得K=9的Viterbi译码算法可在以单片XC4010 FPGA为主的器件上实现,其性能指标符合CD-MA数字移动通信IS-95标准要求.文中给出了实测的算法性能,讨论了FPGA具体实现问题.

关键词: 数字移动通信, 差错控制, Viterbi译码, FPGA实现

Abstract: This paper deals with the error control problem in digital mobile communications. The scheme which employs the maximum likelihood Viterbi algorithm for decoding the K=9 convolutional data is studied. In this scheme, some efficient methods such as the in-place modification operation for path metrics, the saving of path transition and the circle access for path surving are presented. By using these methods, the RAM size needed for saving metrics and paths and the power consumption are decreased. It is shown that the Viterbi algorithm of K=9 whose performance specifications satify the IS-95 standard can be implemented with a single chip FPGA XC4010. The performance is tested, and the implementation consideration is discussed.

Key words: error controlling, digital mobile communications, Viterbi decoding, FPGA implementation

胡爱群, 庞康, 苏杰. K=9卷积码的Viterbi译码算法及其FPGA实现[J]. 应用科学学报, 1998, 16(2): 149-156.

HU AIQUN, PANG KANG, SU JIE. Viterbi Decoding Algorithm and Its FPGA Implementation for K=9 Convolutional Codes[J]. Journal of Applied Sciences, 1998, 16(2): 149-156.