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应用科学学报 ›› 1999, Vol. 17 ›› Issue (2): 211-215.

• 论文 • 上一篇    下一篇

一种基于最优化模型的数字电路测试生成方法

潘中良1, 张光昭1, 陈光2   

  1. 1. 中山大学;
    2. 电子科技大学
  • 收稿日期:1998-01-05 修回日期:1998-04-14 出版日期:1999-06-30 发布日期:1999-06-30

A Circuit Test Generation Method Based on Optimization

PAN ZHONGLIANG1, ZHANG GUANGZHAO1, CHEN GUANGJU2   

  1. 1. Zhongshan University, Guangzhou 510275;
    2. University of Electronic Science and Technology of China, Chengdu 610054
  • Received:1998-01-05 Revised:1998-04-14 Online:1999-06-30 Published:1999-06-30

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73

被引次数

2

摘要： 基于基本门电路的特征函数及被测电路的约束网络结构模型,首先提出一种用于数字电路的模拟退火(SA)测试生成算法,然后在SA算法中采用梯度算法的退火梯度法,该方法的特点是具有全局收敛性和较高的计算效率,它不仅加速了数字电路的测试生成过程,而且也可应用于其他类型的优化问题.

关键词: 测试生成, 最优化, 模拟退火, 梯度算法, 数字电路

Abstract: Test pattern generation for integrated circuits is an important and complex problem. An optimization method of test pattern generation for digital circuits is proposed in this paper. In the method, a characteristic function for each basic gate circuit and the constrained network for the circuit under test (CUT) are defined, the test patterns for a fault can be obtained by means of a simulated annealing algorithm. A new algorithm, namely annealing descent algorithm(SDA), is presented, which enhance the performance of conventional simulated annealing method, and accelerate the test generation process further.

Key words: digital circuits, test generation, optimization, descent algorthms, simulated annealing