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应用科学学报 ›› 2004, Vol. 22 ›› Issue (2): 162-166.

• 论文 • 上一篇    下一篇

PDP扫描驱动芯片的新型200VP沟功率MOSFET及工艺研究

易扬波, 孙伟锋, 孙智林, 陈畅, 陆生礼   

  1. 东南大学国家专用集成电路系统工程技术研究中心 江苏南京 210096
  • 收稿日期:2003-01-17 修回日期:2003-06-17 出版日期:2004-06-30 发布日期:2004-06-30
  • 作者简介:易扬波(1978-),男,湖南慈利人,硕士生.
  • 基金资助:
    国家高技术研究发展计划(863计划)资助项目(2002AA1Z1550)

A Novel 200V P-Channel Power MOSFET and the Process for the PDP Scan Driver IC

YI Yang-bo, SUN Wei-feng, SUN Zhi-lin, CHEN Chang, LU Sheng-li   

  1. National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
  • Received:2003-01-17 Revised:2003-06-17 Online:2004-06-30 Published:2004-06-30

PDF

88

被引次数

5

摘要： 提出了一种适合PDP扫描驱动芯片的高压P沟道ED-LDMOS器件结构,源漏击穿电压及栅耐压均达到220V以上.通过添加P型扩展阱,能够有效降低P+漏极边缘电场60%,减轻漏极电流汇聚效应,抑制寄生双极型晶体管开启,从而原器件开启态耐压(180V)提高了40V;同时设计了能与0.6μm标准低压CMOS工艺完全兼容的制备工艺,特别提出一种厚栅氧与多晶栅的刻蚀方法——余量刻蚀法,有效防止由于光刻误差引起的栅源短路击穿.

关键词: 功率器件, 半导体工艺, 功率集成电路

Abstract: In this paper, a novel P-channel high voltage extended drain lateral double-diffused MOSFET(ED-LDMOS) is proposed for the PDP scan driver IC. The breakdown voltage between source and drain is above 220V and the gate also has a breakdown voltage of 220V. The extended drain structure can reduce the peak electric field by 60% and the current crowding effect around P~+ drain, so it can suppress the turn-on of the parasitic bipolar transistor. Also an isolated N-well near P~+ source and N~+ buried layer at the bottom of the device are added to further reduce the leak current and improve the breakdown voltage by 40V. The process is compatible with the 0.6μm standard LV-CMOS process. A margin etch method for the thick gate oxide film is specially proposed. It can prevent a short circuit between the gate and source caused by photolithography offsets.

Key words: power device, semiconductor process, power IC

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