Abstract: In this paper, a novel P-channel high voltage extended drain lateral double-diffused MOSFET(ED-LDMOS) is proposed for the PDP scan driver IC. The breakdown voltage between source and drain is above 220V and the gate also has a breakdown voltage of 220V. The extended drain structure can reduce the peak electric field by 60% and the current crowding effect around P~+ drain, so it can suppress the turn-on of the parasitic bipolar transistor. Also an isolated N-well near P~+ source and N~+ buried layer at the bottom of the device are added to further reduce the leak current and improve the breakdown voltage by 40V. The process is compatible with the 0.6μm standard LV-CMOS process. A margin etch method for the thick gate oxide film is specially proposed. It can prevent a short circuit between the gate and source caused by photolithography offsets.

Key words: power device, semiconductor process, power IC