Abstract:

To study low cost and low power applications, we propose a decoding architecture with low resource overhead for multi-edge-type low density parity check (LDPC) codes. The architecture links the check node computed unit and variable node computed unit by cache. The analysis and experiments show that, compared with the traditional partial parallel decoding architecture, the decoding architecture described in this paper cuts about 50% RAM for storing iterative information when the check matrix is random, about 90% MUX for transmitting iterative information, and about 80% variable node computation unit for generating iterative information transmitted form variable nodes to check nodes.

Key words: multi-edge-type, low density parity check codes, decoder, cache, field programmable gate array