Abstract: With the fast growing portable-electronics market and stricter requirement of the wafer test, the power consumption problem of built-in self-test (BIST) has attracted more and more attention. In this paper, a parameter optimization algorithm that can lower the peak power during test application has been proposed. Experiment results show that peak power is reduced considerably with no extra silicon overhead of test logic on the condition that fault coverage is guaranteed.

Key words: low power, linear feedback shift register, built-in self-test